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| FDS6930B Dual N-Channel Logic Level PowerTrench(R) MOSFET June 2005 FDS6930B Dual N-Channel Logic Level PowerTrench(R) MOSFET Features 5.5 A, 30 V. RDS(ON) = 38 m @ VGS = 10 V RDS(ON) = 50 m @ VGS = 4.5 V Fast switching speed Low gate charge High performance trench technology for extremely low RDS(ON) High power and current handling capability General Description These N-Channel Logic Level MOSFETs are produced using Fairchild Semiconductor's advanced PowerTrench process that has been especially tailored to minimize the on-state resistance and yet maintain superior switching performance. These devices are well suited for low voltage and battery powered applications where low in-line power loss and fast switching are required. D2 D1 D1 D2 5 6 4 3 2 1 SO-8 Pin 1 S1 G1 S2 G2 7 8 Absolute Maximum Ratings TA = 25C unless otherwise noted Symbol VDSS VGSS ID PD Drain-Source Voltage Gate-Source Voltage Drain Current - Continuous - Pulsed Power Dissipation for Dual Operation Power Dissipation for Single Operation (Note 1) (Note 1a) (Note 1b) (Note 1c) TJ, TSTG RJA RJC Operating and Storage Junction Temperature Range (Note 1a) Parameter Ratings 30 20 5.5 20 2 1.6 1 0.9 -55 to 150 Units V V A W C C/W C/W Thermal Characteristics Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case (Note 1a) (Note 1) 78 40 Package Marking and Ordering Information Device Marking FDS6930B Device FDS6930B Reel Size 13" Tape width 12mm Quantity 2500 units (c)2005 Fairchild Semiconductor Corporation 1 www.fairchildsemi.com FDS6930B Rev. A FDS6930B Dual N-Channel Logic Level PowerTrench(R) MOSFET Electrical Characteristics TA = 25C unless otherwise noted Symbol Off Characteristics BVDSS BVDSS TJ IDSS IGSS VGS(th) VGS(th) TJ RDS(on) Drain-Source Breakdown Voltage Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current Gate-Source Leakage (Note 2) Parameter Test Conditions VGS = 0 V, ID = 250 A ID = 250 A, Referenced to 25C VDS = 24 V, VGS = 0 V VDS = 24 V, VGS = 0 V, TJ = 55C VGS = 20 V, VDS = 0 V VDS = VGS, ID = 250 A ID = 250 A, Referenced to 25C VGS = 10 V, ID = 5.5 A VGS = 4.5 V, ID = 4.8 A VGS = 10 V, ID = 5.5 A, TJ = 125C VGS = 10 V, VDS = 5 V VDS = 5 V, ID = 5.5 A VDS = 15 V, V GS = 0 V, f = 1.0 MHz Min 30 Typ Max Units V 26 1 10 100 1 1.9 -4.6 31 40 45 20 19 38 50 62 3 mV/C A nA On Characteristics Gate Threshold Voltage Gate Threshold Voltage Temperature Coefficient Static Drain-Source On-Resistance On-State Drain Current Forward Transconductance V mV/C m ID(on) gFS Ciss Coss Crss RG td(on) tr td(off) tf Qg Qgs Qgd IS VSD trr Qrr Notes: A S Dynamic Characteristics Input Capacitance Output Capacitance Reverse Transfer Capacitance Gate Resistance (Note 2) 310 90 40 412 120 60 pF pF pF VGS = 15 mV, f = 1.0 MHz VDD = 15 V, ID = 1 A, VGS = 10 V, RGEN = 6 1.9 Switching Characteristics Turn-On Delay Time Turn-On Rise Time Turn-Off Delay Time Turn-Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge 6 6 16 2 12 12 28 4 3.8 ns ns ns ns nC nC nC VDS = 5 V, ID = 5.5 A, VGS = 5 V 2.7 1.0 0.7 Drain-Source Diode Characteristics and Maximum Ratings Maximum Continuous Drain-Source Diode Forward Current Drain-Source Diode Forward Voltage Diode Reverse Recovery Time (note3) Diode Reverse Recovery Charge VGS = 0 V, IS = 1.3 A (Note 2) IF = 5.5 A, diF/dt = 100 A/s 0.8 16 6 1.3 1.2 32 A V nS nC 1. RJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RJC is guaranteed by design while RCA is determined by the user's board design. a) 78C/W when mounted on a 0.5 in2 pad of 2 oz copper b) 125C/W when mounted on a 0.02 in2 pad of 2 oz copper c) 135C/W when mounted on a minimum pad. Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300s, Duty Cycle < 2.0% 3. Trr parameter will not be subjected to 100% production testing. 2 FDS6930B Rev. A www.fairchildsemi.com FDS6930B Dual N-Channel Logic Level PowerTrench(R) MOSFET Typical Characteristics 20 2 VGS = 10V 16 4.0V RDS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE 1.8 ID, DRAIN CURRENT (A) 6.0V 12 4.5V VGS = 3.5V 1.6 3.5V 1.4 4.0V 4.5V 5.0V 6.0V 10.0V 8 3.0V 4 1.2 1 0 0 0.5 1 1.5 VDS, DRAIN TO SOURCE VOLTAGE (V) 2 0.8 0 4 8 12 ID, DRAIN CURRENT (A) 16 20 Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. 0.12 1.6 RDS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE 1.4 RDS(ON), ON-RESISTANCE (OHM) ID = 5.5A VGS = 10.0V ID = 2.75A 0.1 1.2 0.08 TA = 125C 0.06 1 0.8 0.04 TA = 25C 0.02 0.6 -50 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (oC) 125 150 2 4 6 8 VGS, GATE TO SOURCE VOLTAGE (V) 10 Figure 3. On-Resistance Variation with Temperature. 20 Figure 4. On-Resistance Variation with Gate-to-Source Voltage. 100 IS, REVERSE DRAIN CURRENT (A) VDS = 5V 16 VGS = 0V 10 TA = 125C 25C -55C 0.01 I D, DRAIN CURRENT (A) 1 12 0.1 8 TA = 125 C 4 25C 0 1 2 3 4 VGS, GATE TO SOURCE VOLTAGE (V) 5 -55C 0.001 0.0001 0 0.2 0.4 0.6 0.8 1 VSD, BODY DIODE FORWARD VOLTAGE (V) 1.2 Figure 5. Transfer Characteristics. Figure 6. Body Diode Forward Voltage Variation with Source Current and Temperature. 3 FDS6930B Rev. A www.fairchildsemi.com FDS6930B Dual N-Channel Logic Level PowerTrench(R) MOSFET Typical Characteristics 10 ID = 5.5A 500 f = 1 MHz VGS = 0 V 400 15V VDS = 5V VGS, GATE-SOURCE VOLTAGE (V) 8 CAPACITANCE (pF) 6 10V 4 300 Ciss 200 Coss 100 Crss 2 0 0 1 2 3 4 Qg, GATE CHARGE (nC) 5 6 0 0 5 10 15 VDS, DRAIN TO SOURCE VOLTAGE (V) 20 Figure 7. Gate Charge Characteristics. 100 100s P(pk), PEAK TRANSIENT POWER (W) 50 Figure 8. Capacitance Characteristics. ID, DRAIN CURRENT (A) 10 RDS(ON) LIMIT 40 1ms 10ms 100ms 1s SINGLE PULSE RJA = 135C/W TA = 25C 30 1 DC VGS = 10.0V SINGLE PULSE RJA = 135C/W TA = 25C 10s 20 0.1 10 0.01 0.01 0.1 1 10 VDS, DRAIN-SOURCE VOLTAGE (V) 100 0 0.001 0.01 0.1 1 t1, TIME (sec) 10 100 Figure 9. Maximum Safe Operating Area. Figure 10. Single Pulse Maximum Power Dissipation. r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 1 D = 0.5 0.2 RJA(t) = r(t) * RJA RJA = 135C/W P(pk) t1 t2 TJ - TA = P * RJA(t) Duty Cycle, D = t1 / t2 0.1 0.1 0.05 0.02 0.01 0.01 SINGLE PULSE 0.001 0.0001 0.001 0.01 0.1 t1, TIME (sec) 1 10 100 1000 Figure 11. Transient Thermal Response Curve. Thermal characterization performed using the conditions described in Note 1c. Transient thermal response will change depending on the circuit board design. 4 FDS6930B Rev. A www.fairchildsemi.com TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACExTM FAST(R) ActiveArrayTM FASTrTM BottomlessTM FPSTM Build it NowTM FRFETTM CoolFETTM GlobalOptoisolatorTM CROSSVOLTTM GTOTM DOMETM HiSeCTM EcoSPARKTM I2CTM E2CMOSTM i-LoTM EnSignaTM ImpliedDisconnectTM FACTTM IntelliMAXTM FACT Quiet SeriesTM Across the board. Around the world.TM The Power Franchise(R) Programmable Active DroopTM DISCLAIMER ISOPLANARTM LittleFETTM MICROCOUPLERTM MicroFETTM MicroPakTM MICROWIRETM MSXTM MSXProTM OCXTM OCXProTM OPTOLOGIC(R) OPTOPLANARTM PACMANTM POPTM Power247TM PowerEdgeTM PowerSaverTM PowerTrench(R) QFET(R) QSTM QT OptoelectronicsTM Quiet SeriesTM RapidConfigureTM RapidConnectTM SerDesTM SILENT SWITCHER(R) SMART STARTTM SPMTM StealthTM SuperFETTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogic(R) TINYOPTOTM TruTranslationTM UHCTM UltraFET(R) UniFETTM VCXTM WireTM FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component is any component of a life 1. Life support devices or systems are devices or support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Preliminary First Production No Identification Needed Full Production Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I16 |
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